The invention relates to a sensing circuit, and more particularly, to a sensing circuit for a single bit-line semiconductor memory device.
Memory is one of the key components in electronic equipment on the market. Memory can be divided into two groups by the way the memory stores information: volatile memory and nonvolatile memory. A memory is called a volatile memory because it is the kind of storage device that when the power is cut, digital data stored in the volatile memory will be lost. For example, products such as DRAM or SDRAM belong to the volatile memory group. The advantage of volatile memory is that the access speed is fast, so it is often used as a buffer between a high speed processing unit and other circuits. But the disadvantage of volatile memory is that it cannot keep the data stored in it after the power is cut. On the other hand, nonvolatile memory can keep data stored in it even after the power is cut. However, the disadvantage of nonvolatile memory is that the access speed is slower than volatile memory. Products such as ROM or flash memory belong to the nonvolatile memory group.
The application of volatile memory is very broad, in addition to being used in personal computers as a data storage device, volatile memory is also used for storing digital data in devices such as cell phones, personal digital assistants, and laptop computers.
Generally speaking, a memory installed in an electronic device can perform basic mode operations according to a controlling signal from the electronic device, such as write mode, erase mode and read mode. In write mode, the electronic device writes digital data into specific storage addresses of the memory according the controlling signal; in erase mode the electronic device erases digital data at specific storage addresses of the memory according the controlling signal; in read mode the electronic device reads digital data out from specific storage address of the memory according the controlling signal.
A memory always includes a sensing circuit (or a sensing amplifier) for reading out data at specific storing addresses in the memory according to instruction of controlling signal. The sensing circuit is electrically connected to a memory cell array in the memory used for storing digital data. In the 1998 “Symposium on VLSI Circuits Digest of Technical Papers”, page 158 to page 161, a sensing circuit is disclosed. Please refer to FIG. 1, which is a circuit diagram of a single bit-line ROM sensing circuit of the related art. In FIG. 1, the ROM contains a sensing circuit 10 and a memory cell array 20. Wherein the memory cell array 20 includes a plurality of memory cells 22, the addresses of the memory cells 22 is defined by a plurality of word lines WL1˜WLn and a plurality of bit lines BL1˜BLn, that is, at the cross point of each word line and each bit line there is a memory cell 22 electrically connected to the word line and the bit line. In FIG. 1, each memory cell 22 is an NMOS transistor, the drain being electrically connected to the bit line, the gate being electrically to the word line, and the source being electrically connected to ground.
Using a bit line BL1 as an example, the bit line BL1 is electrically connected to the sensing circuit 10. The sensing circuit 10 contains a first pre-charging module 12, a selecting module 14, a second pre-charging module 16, and a sensing-locking module 18. The first pre-charging module 12 is electrically connected to the bit line BL1 for pre-charging the bit line BL1. In FIG. 1, the first pre-charging module 12 is an NMOS transistor for pre-charging the bit line BL1 to 0V, the drain being electrically connected to the bit line BL1, the gate being electrically connected to a controlling signal Y1b. The selecting module 14 is electrically connected between the bit line BL1 and a data line DL, for passing a signal on the bit line BL1 to the data line DL according to the controlling signals Y1 and Y1b. In FIG. 1, the selecting module 14 is a transmission gate containing an NMOS transistor and a PMOS transistor, and the turn on and turn off of the transmission gate is controlled by the controlling signals Y1 and Y1b. The second pre-charging module 16 is used for pre-charging the data line DL. In FIG. 1, the second pre-charging module 16 is a PMOS transistor, the drain being electrically connected to the data line DL, the gate being electrically connected to a controlling signal PRE, the source being electrically connected to a power supply voltage VDD, for pre-charging the data line DL to VDD. The sensing-locking module 18 is electrically connected to the data line DL and is for sensing the digital signal on the data line DL and locking to the digital signal to generate an output signal on the output signal line OUT.
Please notice that the above description only uses one bit line BL1 as an example, in reality there are more than one bit line being electrically connected to the same data line DL via the selecting module 14, as shown in FIG. 1.
Described next is the job flow illustrating how the ROM in FIG. 1 uses the sensing circuit 10 to read data. When the ROM reads digital data stored in the memory cell array 20, a controlling unit (not shown in FIG. 1) uses the controlling signals to control the first pre-charging module to pre-charge the bit line (such as bit line BL1) corresponding to the address of the desired data to 0V, and then uses the controlling signal Y1 and Y1B to turn on the selecting module 14. A controlling signal PRE is next used to control the second pre-charging module 16 to pre-charge the data line DL and the bit line BL1 to VDD. Finally, the controlling unit inputs a high voltage to the word line (such as word line WL1) corresponding to the address of the desired data such that data stored in the selected memory cell 22 (in this example, the memory cell located at the cross point of bit line BL1 and word line WL1) is output to the output line OUT via the bit line BL1, the data line DL, and the sensing-locking module 18.
However, there is a significant flaw in the sensing circuit 10 shown in FIG. 1. When the memory cell 22 first stores digital value 0, the memory cell 22 is at low threshold voltage state. To read out the “0” stored in the memory cell 22, the selected bit line BL1 and data line DL must be pre-charged to VDD and discharged to 0V via the path to ground formed by the memory cell 22 in a turned on state, ending the reading process. Because the bit line BL1 is electrically connected to multiple memory cells 22 and the data line DL is electrically connected to multiple selecting modules 14, the bit line BL1 and the data line DL combine with a very large parasitic capacitance because they have a very large layout area. Therefore, during the process of reading the logic value “0”, both the second pre-charging module 16 and the selected memory cell 22 must charge (or discharge) the bit line BL1 and the data line DL, which have a very large parasitic capacitance. This causes a direct constraint on the speed of the ROM. Additionally, charging (or discharging) the bit line BL1 and the data line DL with a very large parasitic capacitance consumes a great amount of power.